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d a t a sh eet preliminary speci?cation file under integrated circuits, ic01 may 1994 integrated circuits philips semiconductors saa2003 stereo filter and codec
may 1994 2 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 features single-chip stereo filter and codec wide operating voltage range: 2.7 to 5.5 v low-power consumption: 98 mw; 3.0 v sleep mode for low power and low electromagnetic interference (emi) transparent serial audio data mode in sleep iec 958 digital output peak level detector for start of track detection or vu meter versatile fade processor; slow/fast fade, mute, 12 db attenuation serial audio interface for i 2 s or eiaj formats error concealment three-wire l3 bus microcontroller interface three sample rates: C 32 khz C 44.1 khz C 48 khz internal or external clock source three programmable outputs small surface mounted package (sot307). general description the saa2003 performs the sub-band filtering and audio frame codec functions in the precision adaptive sub-band coding (pasc) system. it can be used as a stand-alone decoder for playback only applications, but requires the addition of an adaptive allocation and scale factor processor (saa2013) in order to perform pasc encoding in a dcc record system. ordering information note 1. when using reflow soldering it is recommended that the dry packing instructions in the quality reference pocketbook are followed. the pocketbook can be ordered using the code 9398 510 34011. extended type number package pins pin position material code SAA2003H 44 qfp (1) plastic sot307
may 1994 3 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 block diagram fig.1 block diagram. handbook, full pagewidth mbd618 clock generator x22in x22out x24in x24out clk22 clk24 x256 fs256 fs128 fs256 6.15 mhz sbmclk 19 20 test0 test1 651094113738 287 39 v dd1 v dd2 v dd3 iec 958 output baseband serial interface and peak detector 29 36 35 34 33 stereo subband filter processor pasc codec processor subband serial interface 22 26 25 24 23 sbws sbcl sbda sbdir sbef iecop ws sck sd1 sd2 21 13 12 urda reset sleep l3data l3mode syncdai ltcnt0 l3clk fdir ltcnt1 microcontroller interface and control fdao fdws fdcl fsync 27 8 40 v ss1 v ss2 v ss3 43 2 3 44 1 fdai filtered data interface saa2003 32 31 30 mutedac attdac deemdac 17 18 14 15 16 41 42
may 1994 4 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 pinning symbol pin description type fdai 1 ?ltered data input from saa2013 i fdcl 2 ?ltered data bit clock o fdws 3 ?ltered data word select o clk22 4 22.5792 mhz buffered clock output o x22out 5 22.5792 mhz crystal output o x22in 6 22.5792 mhz crystal input i v dd2 7 supply voltage (clock oscillator) - v ss2 8 supply ground (clock oscillator) - x24out 9 24.576 mhz crystal output o x24in 10 24.576 mhz crystal input i clk24 11 24.576 mhz buffered clock output o sleep 12 sleep mode; device inactive i reset 13 device reset i l3data 14 3-wire interface; serial data i/o l3clk 15 3-wire interface; bit clock i l3mode 16 3-wire interface; mode control i ltcnt0 17 lt interface; control bit 0 i ltcnt1 18 lt interface; control bit 1 i test0 19 test mode select i test1 20 test mode select i urda 21 unreliable data ?ag from drive processor i sbdir 22 sub-band data direction i sbda 23 sub-band serial data i/o sbcl 24 sub-band bit clock i/o sbws 25 sub-band word select i/o sbef 26 sub-band error ?ag from drive processor i v ss1 27 digital supply ground - v dd1 28 digital supply voltage - iecop 29 iec 958 digital audio output o deemdac 30 dac control or general purpose output o attdac 31 dac control or general purpose output o mutedac 32 dac control or general purpose output o sd2 33 serial audio data to dac o sd1 34 serial audio data to/from daio and dac i/o sck 35 serial audio data bit clock i/o ws 36 serial audio data word select i/o x256 37 master audio clock from external source i fs256 38 master audio clock at 256 times sample frequency o v dd3 39 supply voltage (fs256) - v ss3 40 supply ground (fs256) -
may 1994 5 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 fdir 41 ?lter direction; encode or decode o syncdai 42 settings synchronization for daio o fsync 43 sub-band 0 sample synchronization for saa2013 o fdao 44 ?ltered data output to saa2013 o symbol pin description type fig.2 pin configuration. 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 sd2 mutedac attdac deemdac iecop v sbef sbws sbcl sbda ss1 v dd1 fdao fsync syncdai fdir ss3 dd3 fs256 x256 ws sck sd1 v v fdai fdcl fdws clk22 x22out x22in dd2 ss2 x24out x24in clk24 v v saa2003 sleep reset l3data l3clk l3mode ltcnt0 ltcnt1 test0 test1 urda sbdir mbd619
may 1994 6 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 functional description handbook, full pagewidth mbd620 tape drive processing dac tda1305 adc saa7366 analog output digital audio i/o tda1315 iec958 analog input audio in/out pasc processor i s 2 l r l r sfc3 saa2003 stereo filter codec adas3 saa2013 adaptive allocation filtered i s 2 sub-band i s 2 baseband drp saa2023 or saa3323 drive processor ram 41464 buffer 64k x 4 rdamp tda1380 read amp. wramp tda1381 write amp. fixed head tape capstan drive speed control mechanics drivers analog cc l output analog cc r output system microcontroller system control search data detect switch fig.3 dcc system block diagram.
may 1994 7 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 pasc processor the pasc processor is a dedicated digital signal processor (dsp) engine which efficiently codes digital audio data at a bit rate of 384 kbits/s without affecting the sound quality. this is achieved using an efficient adaptive data notation and by only encoding the information which can be heard by the human ear. the audio data is split into 32 equal sub-bands during encoding. for each of the sub-bands a masking threshold is calculated. the samples from each of the sub-bands are included in the pasc data with an accuracy that is determined by the available bit-pool and by the difference between the signal power and the masking threshold for that sub-band. the stereo filter codec performs the splitting (encoding) and reconstruction (decoding), including the necessary formatting functions. during encoding, the adaptive allocation and scaling circuit calculates the required accuracy (bit allocation) and scale factors of the sub-band samples. e ncoding ( see f ig .4) the incoming serial audio data is filtered into 32 sub-bands for left and right (i and ii) channels using the stereo filter part of the saa2003. a pasc frame is made up of left and right (i and ii) audio data for 12 samples from each of the 32 sub-bands, a total of 768 audio samples. for every pasc frame the saa2013 calculates a bit allocation and scale factor table which is transferred to the saa2003. all the samples in a frame are scaled in accordance with the scale factor calculated by the saa2013. once scaled the samples are re-quantized to reduce the number of bits to correspond with the allocation table calculated by the saa2013. synchronization, allocation and scale factor information is then added to provide a fully encoded pasc data signal. these frames of data are then sent to the drive processor ic (saa2023 or saa3323). fig.4 encoding mode. handbook, full pagewidth mlb764 formatter pasc output data sub-band samples allocation and scale factor information table scaling and quanti zation sync and coding information from saa2013 allocation information and scale factor indices quantified samples sub-band filter baseband samples d ecoding ( see f ig .5) in decoding mode the saa2003 synchronizes and recovers frames of data from the drive processor. the recovered allocation data and the scale factors are used to correctly re-quantize and re-scale the pasc sub-band samples. the decoded sub-band samples, which are represented in 24-bits twos complement notation, are reconstructed by the sub-band filters into a single complete digital audio signal.
may 1994 8 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 crystal oscillators the recommended crystal oscillator configuration is shown in fig.6. the specified component values only apply to crystals with a low equivalent series resistance of <40 w . system reset reset must be active from system power-up for >1 ms. reset must also be active for >1 ms after the falling edge of sleep as shown in fig.7. fig.5 decoding mode. handbook, full pagewidth mea804 - 1 de formatter pasc data input scale factor scale factor array and allocation de-quantization control multiply allocation sync/coding quantified samples sub-band samples output control sub-band filter baseband samples saa2003 40 41 42 43 r1 1 m w 22.5792 mhz x1 r2 220 w c2 33 pf c1 33 pf r4 1 m w 24.576 mhz x2 r3 1 k w c3 33 pf c4 33 pf x22in x22out x24in x24out mbd621 fig.6 crystal oscillator components.
may 1994 9 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 fig.7 reset and sleep timing. handbook, full pagewidth mbd622 active active active active static t 1 mode 1 mode 2 mode 3 mode 4 t 3 t 2 standby reset clk24/clk22 i/o's table 1 reset and sleep timing modes (see fig.7). sleep mode a high input applied to the sleep pin halts all internally generated clock signals. if the transparent mode of the serial audio interface is set before entering sleep, the data at the x256 external clock input is sent to the fs256 output and the data at sd1 input is sent to the sd2 output. if transparent mode is not set, these two outputs are high impedance during sleep mode. the iecop pin is set to high impedance during sleep mode, unless the transparent mode is selected and ws-sel is set. mode description timing min. max. unit mode1 standby stage 1; clocks still running t 1 400 - ns mode2 standby mode; clocks stopped t 2 0 - ns mode3 clocks running; reset active t 3 1 - ms mode4 normal operational mode ---
may 1994 10 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 table 2 transparent mode function in sleep. notes 1. transparent mode is controlled by bit 3 of the serial audio data interface mode control register. 2. ws-sel is controlled by bit 3 of the codec extended settings register. serial audio interface the signals between the saa2003 and the serial audio input/output are shown in table 3. table 3 interface signals between saa2003 and serial audio input/output. the word select (ws) line indicates the channel being transmitted (either left or right; i or ii) and is equal in frequency to the sampling frequency (f s ). operating at a frequency of 64 f s , the bit clock (sck) dictates that each ws period contains 64 sd1 or sd2 data bits. of these bits a maximum of 36 are used to transfer data (samples may have a length up to 18 bits). samples are transferred most significant bit (msb) first. both ws and sd1/sd2 change state at the negative edge of sck. the serial audio data is transferred between the saa2003 and the input/output using either the standard i 2 s (default) as shown in fig.8 or the eiaj format as shown in fig.9. pin transparent mode (1) ws-sel (2) pin function fs256 1 x fs256 fs256 0 x high impedance sd2 1 x sd1 sd2 0 x high impedance iecop 0 x high impedance iecop 1 0 high impedance iecop 1 1 ws pin input/output function frequency ws bi-directional audio data word select f s sck bi-directional audio data bit clock 64f s sd1 bi-directional serial audio data to/from daio and adc - sd2 output audio serial data to dac - fdir output pasc mode encode/decode - iecop output alternative serial data word select for sd2 -
may 1994 11 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 mbd623 0123 17 18 32 33 34 35 31 49 50 63012 lsb msb lsb msb msb left channel data right channel data 0123 12 13 16 17 18 19 15 28 29 31012 msb lsb msb msb left channel data right channel data 14 30 lsb sd1/ sd2 sws scl sd1/ sd2 sws scl fig.8 serial audio interface sd1/sd2; i 2 s data format. a. b. a. master and slave modes; 18 bits. b. slave mode only; 16 bits.
may 1994 12 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 mbd624 012 14 15 30 31 32 33 46 47 62 63 0 1 lsb msb msb left channel data right channel data sd1/ sd2 sws scl 2 msb msb lsb msb 012 16 17 30 31 32 33 48 49 62 63 0 1 lsb msb msb left channel data right channel data sd1/ sd2 sws scl 2 msb msb lsb msb fig.9 serial audio interface sd1; eiaj data format. a. b. a. master mode; 18 bits. b. master mode (eiaj); 16 bits.
may 1994 13 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 s erial audio interface data formats in encoding mode in encoding mode, the serial audio data input for the pasc processor is taken from the sd1 pin. this data is scaled by the fade processor before being sent to the pasc processor. the output from the fade processor is sent in parallel to the sd2 output. both i 2 s and eiaj formats are supported. table 4 serial audio data interface formats in encoding mode. note 1. if sd1 is used in eiaj mode, and the data from sd2 is required, the iecop can be re-programmed to provide a suitable i 2 s ws signal for sd2. the iec 958 output is not available in this mode. s erial audio interface data formats in decoding mode in decoding mode, the output from the pasc processor, connected via the fade processor, is present at both sd1 and sd2. both i 2 s and eiaj formats are supported. table 5 sd1/sd2 output decoding formats. note 1. the sub-band filter performs rounding to 16 or 18 bits according to the operating mode of the interface. s erial audio interface mode control the operating mode of the interface is programmed by the extended settings registers as shown in table 6. sd1 input sd2 output format master/slave resolution format resolution i 2 s master 18 bit i 2 s 18 bit i 2 s slave 18 bit i 2 s 18 bit i 2 s master 16 bit i 2 s 18 bit i 2 s slave 16 bit i 2 s 16 bit eiaj (1) master 18 bit i 2 s 18 bit eiaj (1) slave 18 bit i 2 s 18 bit eiaj (1) master 16 bit i 2 s 18 bit eiaj (1) slave 16 bit i 2 s 18 bit format master/slave resolution (1) i 2 s master 18 bit i 2 s slave 18 bit i 2 s master 16 bit i 2 s slave 16 bit eiaj master 18 bit eiaj master 16 bit
may 1994 14 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 table 6 extended settings register. filtered data interface the filtered data interface transfers the sub-band filtered data between the stereo filter codec and adaptive allocation and scaling parts of the dcc chip-set, and consists of the signals as shown in table 7. table 7 filtered data interface signals. f iltered data interface format the filtered data is transferred over the interface in accordance with the formats illustrated in figs 10 and 11. a3 a2 a1 a0 d3 d2 d1 d0 mode 0 0 1 0 x x x 0 16 bit operation; 16 bit rounding 0 0 1 0 x x x 1 18 bit operation; 18 bit rounding 0010xx0xi 2 s data format 0 0 1 0 x x 1 x eiaj data format 0 0 1 0 x 0 x x peak detector input sd1 0 0 1 0 x 1 x x peak detector input sd2 0 0 1 0 0 x x x sd1/fs256 transparent mode disabled 0 0 1 0 1 x x x sd1/fs256 transparent mode enabled pin input/output function frequency fdcl output ?ltered data bit clock 64f s fdws output ?ltered data word select f s fdao output ?ltered data serial output - fdai input ?ltered data serial input - fdir output decode/encode control - fsync output ?ltered data sync signal; band zero - fig.10 transfer of filtered data; saa2003/saa2013. handbook, full pagewidth mlb765 left 32 bits right 7 bits 1 0 2 0 1 0 0 2 3 2 2 2 1 2 0 msb lsb 2 3 2 2 2 1 2 0 msb channel fdws fdcl fdai/ fdao bit :
may 1994 15 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 sub-band serial pasc interface the sub-band serial interface carries the pasc serial data stream between the stereo filter codec and the drive processor part of the dcc chip-set, and consists of the signals as shown in table 8. table 8 sub-band serial pasc interface signals. the saa2003 generates sbws and sbcl in both decode and encoding modes. in decode both signals can be set to inputs (slave mode) by bit 0 of the extended settings register. the filtered data interface timing is always derived from the 24.576 mhz clock, regardless of the audio sampling frequency. table 9 extended settings register. stereo and 2-channel mono encoding modes are available. stereo, joint stereo and 2-channel mono decoding modes are available. in decoding and encoding, 48 khz, 44.1 khz and 32 khz sample frequencies can be used. pin input/output function frequency sbdir input sub-band data direction control - sbda input/output sub-band serial data - 1sbcl input/output sub-band bit clock 768 khz sbws input/output sub-band word select 12 khz sbef input sub-band data error ?ag - urda input unreliable data ?ag - a3 a2 a1 a0 d3 d2 d1 d0 mode 0 0 0 1 x x x 0 slave mode (default) 0 0 0 1 x x x 1 master mode fig.11 transfer of sub-band pasc data. 32 bits 15 bits 1 1 0 1 1 1 2 0 0 0 1 0 2 0 3 1 6 1 7 1 8 sbws sbcl sbda bit : 2 0 2 1 mea649 - 2 msb sbef lsb msb byte 0 byte 1 byte 2 1 9 2 2 1 1 3 1 4 1 5
may 1994 16 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 s ub - band serial pasc interface data format the pasc data is transferred over the interface described above using the format shown in fig.11. each period of sbws spans 64 periods of the bit clock, sbcl, of which 32 sbcl periods are used to transfer pasc data. the 32 data bits transferred in one period of sbws make up a complete sub-band slot, as defined in the dcc standard. the first 16 data bits (0, 1, 2, .., 15) are transferred while sbws is low, and the second 16 data bits (16, 17, 18, .., 31) are transferred while sbws is high. sbef and urda are generated by the drive processor during decode. the presence of the urda flag causes the stereo filter codec to mute the audio output data, and lose audio frame synchronization. the direction of sbda is controlled by the sbdir input, which is connected to the drive processor. syncdai signal syncdai is a pulse of fixed duration which is generated by the saa2003 when any of the following conditions occur: change of bit rate change of sampling frequency change from encode to decode and vice-versa change of fs256 clock source change of i 2 s bus master reset. the syncdai signal is used to synchronize the digital audio input/output interface. audio peak level detector the peak level detector continuously encodes the maximum amplitude of the audio data samples for each audio channel until it is reset by the action of reading out the peak level data. the peak level data can be read by the saa2013, and subsequently by the system microcontroller, or by the microcontroller directly when saa2013 is not used. the peak level data is read via the l3 interface in status read mode. the first 16 bits of status read transfer the status bits of saa2003. the following 32 bits contain the peak level data. the peak level detector is reset when the 32 bits of peak level data are read. in encode, the peak level detector can be used to monitor the data on either sd1 (pre-fade processor) or sd2 (post fade processor). in slave eiaj input modes the peak detection is only possible on output sd2. in decode mode, sd1 must be selected for peak detector input data. handbook, full pagewidth mbd625 8150 71617 30 31 32 33 46 47 l3mode l3clk l3data fig.12 peak level data format during status read.
may 1994 17 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 audio fade processor the fade processor is controlled by the system microcontroller. it achieves level control, or fading, by multiplying the audio samples with a 17 bit accuracy fade coefficient, which is selected by an 8-bit fade counter. the fade coefficients range from 0 to 1.0 according to a 1 4 cosine function. the attenuation for a particular fade count (fc) is given as follows: where: 0 fc 255. in encode mode, audio samples are taken from input sd1 and scaled before sub-band filter processing, and sent to output sd2. in decode mode, audio samples are scaled following reconstruction by the sub-band filter, and sent to outputs sd1 and sd2. table 10 fade processor operating modes. f ade processor mode control the operating mode of the fade processor is controlled by two extended registers table 11 fade processor mode control. f ade rate option the fade rate can be set to either fast or slow modes. in fast mode the attenuation changes rate at one step per audio sample. in slow mode the rate of change of level is controlled by the fade rate bits p3 to p0. in slow mode, the fade counter is stepped up or down according to a clock derived from the ws pin. mode function fade rate controls rate of automatic increments and decrements step down increases attenuation by one increment step up reduces attenuation by one increment full scale sets gain to unity, incrementing from current level automatically mute sets gain to zero, decrementing from current level automatically - 12 db sets gain to - 12 db, decrementing or incrementing from current level automatically a3 a2 a1 a0 d3 d2 d1 d0 mode 0011p3p2p1p0 set fade rate 01000001 step down 01000010 step up 010001x0 full scale slow 010001x1 full scale fast 010010x0 mute slow 010010x1 mute fast 010011x0 - 12 db slow 010011x1 - 12 db fast 01000000no action attenuation (db) 20 log cos C p fc 510 ----------------- - ? ?? db () =
may 1994 18 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 table 12 fade rate in slow and fast modes. iec 958 output the iecop pin provides an output signal in accordance with the iec 958/spdif digital audio interface format. the function of the iecop pin is programmed by bit 3 of the codec extended settings register; see table 13. table 13 iecop pin control. the iecop output will only function when the saa2003 is in decode mode. the iecop cannot be used when saa2013 is present in the system, unless the saa2013 is in sleep mode. the iecop output is disabled and set to high impedance by a reset. l3 bus the l3 bus is a three-wire clock synchronous data bus common to all ics in the dcc chip-set. it consists of the l3mode, l3clk and l3data connections. the bus has two operating modes: addressing mode; selects the ic for communication and sets type of transfer. data mode; is used to send and receive data and control settings. the l3mode and l3clk lines are driven by the system microcontroller and l3data is a bi-directional line. ltcnt0 and ltcnt1 must be left unconnected when l3 mode is used. for normal use in l3 mode, ltcnt0 and ltcnt1 are held high by internal pull-up resistors. the saa2003 responds to serial addresses as shown in table 14. table 14 saa2003 serial addresses. note 1. d0 and d1 are interpreted as ltcnt0 and ltcnt1 respectively. these two signals control the operation of the interface as given in table 15. mode p3 p2 p1 p0 time per step (ms) time for 256 steps (ms) 32 khz 44.1 khz 48 khz 32 khz 44.1 khz 48 khz fast ---- 31.2 m s 22.7 m s 20.8 m s 8.0 5.8 5.3 slow 00001.0 0.997 1.0 256 255 256 slow 00012.0 1.994 2.0 512 511 512 slow 00114.0 3.988 4.0 1024 1021 1024 slow 01118.0 7.980 8.0 2048 2043 2048 slow 1111 16.0 15.96 16.0 4096 4087 4096 a3 a2 a1 a0 d3 d2 d1 d0 iecop function 00010xxxiec 958 (default) 00011xxxi 2 s word select for sd2 d0 (1) d1 (1) d2 d3 d4 d5 d6 d7 xx000100
may 1994 19 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 table 15 interface modes. table 16 register address settings. note 1. these registers are write only, accessed using the protocol shown in fig.13. operation in lt mode lt interface mode can be selected by writing an extended settings word to the interface mode control register as shown in table 17. table 17 interface mode control register. in lt mode the ltcnt0 and ltcnt1 pins are used, and the l3mode pin becomes lten enable line. l3clk becomes ltclk, and l3data becomes ltdata. d0/ltcnt0 d1/ltcnt1 mode 0 0 extended setting from microcontroller to saa2003 1 0 allocation and scale factor information from saa2013 to saa2003 0 1 codec internal settings from microcontroller to saa2003 1 1 codec status from saa2003 to microcontroller and saa2013 including peak level data a3 a2 a1 a0 register (1) 0000 codec external settings 0001 codec interface mode control 0010 serial audio interface mode control 0011 fade counter rate control 0100 fade counter control a3 a2 a1 a0 d3 d2 d1 d0 mode 0 0 0 1 x x 1 x l3 mode (default) 0 0 0 1 x x 0 x lt mode a ndbook, full pagewidth mbd626 l3mode l3clk l3data d0 d1 d2 d3 a0 a1 a2 a3 fig.13 extended settings protocol.
may 1994 20 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 table 18 summary of address registers. codec internal settings and status the settings register is write only, and the status register is read only. the interface protocols for accessing these registers is shown in figs 14 and 15. address register bit description register explanation 0 external settings register 0 mute dac 1 attenuate dac 2 de-emphasis dac 3 clock ok hold mode 1 codec extended settings 0 slave receive mode 1 l3/lt mode select 2 comparator delay bypass 3 ws/iec 958 selection 2 serial audio mode control 0 18 bit operation 1i 2 s/eiaj format 2 peak detector input select 3 transparent mode 3 fade processor fade rate 0 to 3 rate control, 0 to 15 4 fade processor control 0 to 3 fade command 5 to 15 not used -- fig.14 codec internal settings write transfer. handbook, full pagewidth mbd627 l3mode l3clk l3data 8 9 14 15 0 1 67
may 1994 21 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 mbd628 l3mode l3clk l3data 8150 716 30 17 33 46 47 31 32 fig.15 codec status read transfer.
may 1994 22 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 the codec internal settings register is shown in table 19. table 19 codec internal settings register formats. table 20 codec status register formats. bits description encoding/decoding 15 to 12 bit rate index encoding only 11 and 10 sample frequency encoding only 9 decode mode encoding and decoding 8 external fs256 encoding and decoding 7 2 channel mono encoding only 6 mute sub-band ?lters encoding and decoding 5 external master i 2 s encoding and decoding 4 select channel i/ii decoding only 3 and 2 transparent bits encoding only 1 and 0 emphasis indication encoding only bits description encoding/decoding 15 to 12 bit rate index encoding and decoding 11 and 10 sample frequency encoding and decoding 9 ready-to-receive encoding and decoding 8 not used - 7 and 6 sub-band mode encoding and decoding 5 synchronization decoding only 4 clock ok encoding and decoding 3 and 2 transparent bits encoding and decoding 1 and 0 emphasis indication encoding and decoding 16 ?rst channel identi?cation - 17 to 31 ?rst channel peak level; lsb ?rst - 32 second channel identi?cation - 33 to 47 second channel peak level; lsb ?rst -
may 1994 23 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 average current consumption the average current consumption is shown in fig.16. fig.16 average current consumption. handbook, halfpage 2.5 3.5 4.5 5.5 80 60 20 0 40 mbd640 i dd (ma) v (v) dd timing diagrams fig.17 serial audio interface timing in decode; master mode. handbook, full pagewidth mbd629 t fs t fh t fl t d1 t d1 t cl t c t ch t h2 t d2 fs256 sck ws, sd1 and sd2
may 1994 24 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 fig.18 serial audio interface timing in encode; master mode. handbook, full pagewidth mlb602 t fs t fh t fl t d1 t d1 t cl t c t ch t h2 t d2 t h1 t su fs256 sck ws and sd2 sd1 fig.19 serial audio interface timing; slave mode. handbook, full pagewidth mbd630 t fs t fh t fl t cl c t ch fs256 sck t h2 sd1, sd2 t h1 t su ws, sd1 t d t
may 1994 25 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 fig.20 serial audio master/slave timing. handbook, full pagewidth mbd631 syncdai t sh t d3 t d2 d4 t t d1 ws, sck (slave to master) ws, sck (slave to master) sd1 a ndbook, full pagewidth mbd632 t fs t fh t fl t d1 t cl t ch t h2 t d2 t h1 t su fs256 fdcl fdws, fdao, fsync fdai t d1 t c fig.21 filtered data interface timing.
may 1994 26 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 fig.22 fsync output timing. handbook, full pagewidth mbd633 fdws sub-band # 0 1 2 29 30 31 0 1 2 3 fsync o k, full pagewidth mbd634 t cl t ch sck t d4 sbws t d2 t d1 (encode) sbws, sbda t d3 (decode) sbda t su1 t h1 t su2 t h2 sbef t c fig.23 sub-band pasc interface timing. h andbook, full pagewidth mbd635 sbcl sbda l3data 0 9 12345678 101112 sbws
may 1994 27 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 handbook, full pagewidth mbd637 t d1 t ch t cl t h2 t su t h1 t d3 t d2 t ml l3mode l3clk l3data (input) l3data (output) fig.24 l3 bus timing; addressing mode. handbook, full pagewidth mbd636 t d1 t ch t cl t h3 t su t h1 t d5 t d3 t d2 t d4 t h2 t ml l3mode l3clk l3data (input) l3data (output) l3mode fig.25 l3 bus timing; data transfer mode.
may 1994 28 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 fig.26 internal/external clock source transition timing. handbook, full pagewidth mbd638 t sh t d2 t d1 external t d5 t d4 internal external internal t d3 fs256 clock source fs256 clock source syncdai fdir fig.27 clk22 and clk24 timing. mbd639 t c24l clk24 t f t r t c24h t c24 t c22l clk22 t f t r t c22h t c22
may 1994 29 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. the input voltage (v i ) may not exceed 6.5 v. 2. equivalent to discharging a 100 pf capacitor through a 1.5 k w resistor. 3. equivalent to discharging a 200 pf capacitor through a 2.5 m h inductor. characteristics t amb = - 40 to 85 c; v dd = 2.7 to 5.5 v; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage - 0.5 +6.5 v v i input voltage note 1 - 0.5 v dd + 0.5 v i i input current - 20 ma v o output voltage - 0.5 +6.5 v i o output current - 20 ma i ddq quiescent supply current clocks stopped - 100 m a t stg storage temperature - 65 +150 c t amb operating ambient temperature - 40 +85 c v es1 electrostatic handling note 2 - 2000 +2000 v v es2 electrostatic handling note 3 - 200 +200 v symbol parameter conditions min. typ. max. unit supply v dd supply voltage 2.7 5.0 5.5 v i dd supply current v dd = 3.0 v - 32.5 35.0 ma v dd = 5.0 v - 68.8 75.0 ma sleep mode; v dd = 5.0 v -- 400 m a inputs fdai, l3clk, urda, sbdir, sbef, x256, sleep and l3mode v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v i li input leakage current v i = 0 to v dd - 10 - +10 m a c i input capacitance -- 10 pf inputs test0 and test1 v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v r i(pd) input pull-down resistance v i = v dd - 50 - k w c i input capacitance -- 10 pf
may 1994 30 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 inputs ltcnt0 and ltcnt1 v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v r i(pu) input pull-up resistance v i = 0 v - 50 - k w c i input capacitance -- 10 pf input reset v tlh threshold voltage low-to-high -- 0.8v dd v v thl threshold voltage high-to-low 0.2v dd -- v v hys hysteresis voltage - 0.33v dd - v c i input capacitance -- 10 pf outputs fdcl, fdws, fdir, fsync, fdao, mutedac, attdac and deemdac v ol low level output voltage i ol = 4 ma 0 - 0.4 v v oh high level output voltage i oh = - 4ma v dd - 0.4 - v dd v c l load capacitance -- 30 pf t r output rise time 0.4 v to v dd - 0.4 v; c l = 30 pf -- 20 ns t f output fall time v dd - 0.4 v to 0.4 v; c l = 30 pf -- 20 ns output clk22 v ol low level output voltage i ol = 4 ma 0 - 0.4 v v oh high level output voltage i oh = - 4ma v dd - 0.4 - v dd v c l load capacitance -- 30 pf t r output rise time 0.4 v to v dd - 0.4 v; c l = 30 pf -- 7ns t f output fall time v dd - 0.4 v to 0.4 v; c l = 30 pf -- 7ns output clk24 v ol low level output voltage i ol = 6 ma 0 - 0.4 v v oh high level output voltage i oh = - 6ma v dd - 0.4 - v dd v c l load capacitance -- 50 pf t r output rise time 0.4 v to v dd - 0.4 v; c l = 50 pf -- 7ns t f output fall time v dd - 0.4 v to 0.4 v; c l = 50 pf -- 7ns symbol parameter conditions min. typ. max. unit
may 1994 31 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 output syncdai v ol low level output voltage i ol = 4 ma 0 - 0.4 v v oh high level output voltage i oh = - 4ma v dd - 0.4 - v dd v c l load capacitance -- 40 pf t r output rise time 0.4 v to v dd - 0.4 v; c l = 40 pf -- 20 ns t f output fall time v dd - 0.4 v to 0.4 v; c l = 40 pf -- 20 ns output fs256 v ol low level output voltage i ol = 6 ma 0 - 0.4 v v oh high level output voltage i oh = - 6ma v dd - 0.4 - v dd v c l load capacitance -- 60 pf t r output rise time 0.4 v to v dd - 0.4 v; c l = 60 pf -- 7ns t f output fall time v dd - 0.4 v to 0.4 v ; c l = 60 pf -- 7ns i li 3-state leakage current v i = 0 to v dd - 10 - +10 m a output sd2 v ol low level output voltage i ol = 4 ma 0 - 0.4 v v oh high level output voltage i oh = - 4ma v dd - 0.4 - v dd v c l load capacitance -- 30 pf t r output rise time 0.4 v to v dd - 0.4 v; c l = 30 pf -- 20 ns t f output fall time v dd - 0.4 v to 0.4 v; c l = 30 pf -- 20 ns i li 3-state leakage current v i = 0 to v dd - 10 - +10 m a output iecop v ol low level output voltage i ol = 4 ma 0 - 0.4 v v oh high level output voltage i oh = - 4ma v dd - 0.4 - v dd v c l load capacitance -- 50 pf t r output rise time 0.4 v to v dd - 0.4 v; c l = 50 pf -- 20 ns t f output fall time v dd - 0.4 v to 0.4 v; c l = 50 pf -- 20 ns i li 3-state leakage current v i = 0 to v dd - 10 - +10 m a symbol parameter conditions min. typ. max. unit
may 1994 32 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 inputs/outputs sbda, sbcl and sbws v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v r i(pd) input pull-down resistance v i = v dd - 50 - k w c i input capacitance -- 10 pf v ol low level output voltage i ol = 4 ma 0 - 0.4 v v oh high level output voltage i oh = - 4ma v dd - 0.4 - v dd v c l load capacitance -- 30 pf t r output rise time 0.4 v to v dd - 0.4 v; c l = 30 pf -- 20 ns t f output fall time v dd - 0.4 v to 0.4 v; c l = 30 pf -- 20 ns inputs/outputs sd1, sck and ws v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v r i(pd) input pull-down resistance v i = v dd - 50 - k w c i input capacitance -- 10 pf v ol low level output voltage i ol = 4 ma 0 - 0.4 v v oh high level output voltage i oh = - 4ma v dd - 0.4 - v dd v c l load capacitance -- 50 pf t r output rise time 0.4 v to v dd - 0.4 v; c l = 50 pf -- 20 ns t f output fall time v dd - 0.4 v to 0.4 v; c l = 50 pf -- 20 ns input/output l3data v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v c i input capacitance -- 10 pf v ol low level output voltage i ol = 4 ma 0 - 0.4 v v oh high level output voltage i oh = - 4ma v dd - 0.4 - v dd v c l load capacitance -- 60 pf t r output rise time 0.4 v to v dd - 0.4 v; c l = 60 pf -- 20 ns t f output fall time v dd - 0.4 v to 0.4 v; c l = 60 pf -- 20 ns input x22in (external clock) v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v i li input leakage current - 10 - +10 m a c i input capacitance -- 10 pf symbol parameter conditions min. typ. max. unit
may 1994 33 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 output x22out f xtal crystal frequency note 1 - 22.5792 - mhz g m transconductance 1.5 -- ms g v small signal voltage gain g v = g m r o 3.5 -- c fb feedback capacitance -- 5pf c o output capacitance -- 10 pf input x24in (external clock) v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v i li input leakage current - 10 - +10 m a c i input capacitance -- 10 pf output x24out f xtal crystal frequency note 1 - 24.567 - mhz g m transconductance 1.5 -- ms g v small signal voltage gain g v = g m r o 3.5 -- c fb feedback capacitance -- 5pf c o output capacitance -- 10 pf input x256 f i input frequency f s = 48 khz - 12.288 - mhz f s = 44.1 khz - 11.2896 - mhz f s = 32 khz - 8.192 - mhz t ch high time 35 -- ns t cl low time 35 -- ns clk22 and clk24 timing; fig.27 o utput clk24 f o output frequency c l = 50 pf - 24.576 - mhz t c24h high time c l = 50 pf 12 -- ns t c24l low time c l = 50 pf 12 -- ns t r rise time c l = 50 pf -- 7ns t f fall time c l = 50 pf -- 7ns o utput clk22 f o output frequency c l = 30 pf - 22.5792 - mhz t c22h high time c l = 30 pf 11 -- ns t c22l low time c l = 30 pf 11 -- ns t r rise time c l = 30 pf -- 7ns t f fall time c l = 30 pf -- 7ns symbol parameter conditions min. typ. max. unit
may 1994 34 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 drive processing interface timing; see fig.23 t cy sck cycle time - 1302 - ns t ch sck high time 460 651 - ns t cl sck low time 460 651 - ns t d1 sbws and sbda delay time until sck low 20 -- ns t d2 sck delay time until sbws and sbda valid -- 20 ns t su1 sbda input set-up time before sck high 235 -- ns t h1 sbda input hold time after sck high 30 -- ns t su2 set-up time from sck high until sbef valid -- 90 ns t h2 sbef input hold time after sck high 380 -- ns filtered data interface timing; see fig.21 fdcl, fdws, fdai and fdao f 256 fs256 frequency f s = 48 khz - 12.288 - mhz f s = 44.1 khz - 11.2896 - mhz f s = 32 khz - 8.192 - mhz t c fdcl cycle time f s = 48 khz - 325.6 - ns t fh fs256 high time f s = 48 khz; note 2 35 -- ns f s = 44.1 khz; note 2 38 -- ns f s = 32 khz; note 2 75 -- ns t fl fs256 low time f s = 48 khz; note 2 35 -- ns f s = 44.1 khz; note 2 38 -- ns f s = 32 khz; note 2 35 -- ns t d1 fs256 delay time until fdcl transition 0 - 50 ns t ch fdcl high time f s = 48 khz 143 -- ns t cl fdcl low time f s = 48 khz 143 -- ns t h2 fdws, fdao and fsync hold time after fs256 high 0 -- ns t d2 fs256 high delay time until fdws, fdao and fsync valid 0 - 50 ns t su fdai input set-up time before fs256 high 20 -- ns t h1 fdai input hold time after fs256 high 30 -- ns symbol parameter conditions min. typ. max. unit
may 1994 35 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 timing characteristics fdir and syncdai; see fig.26 t sh syncdai high time 1280 -- ns t d1 internal clock delay time after syncdai low 0 -- ns t d2 external clock delay time after syncdai low -- 320 ns t d3 fdir delay time before syncdai high 280 -- ns t d4 external clock delay time before syncdai high -- 320 ns t d5 internal clock delay time before syncdai high 0 -- ns baseband data interface timing characteristics m aster mode ; see f igs 17 and 18 t c sck cycle time f s = 48 khz - 325.6 - ns t ch sck high time f s = 48 khz 143 -- ns t cl sck low time f s = 48 khz 143 -- ns t d1 fs256 high delay time until sck transition 0 - 50 ns t h2 ws, sd1 and sd2 hold time after fs256 high 0 -- ns t d2 fs256 delay time until ws, sd1 and sd2 valid 0 - 50 ns t su sd1 input set-up time before sck high 30 -- ns t h1 sd1 input hold time after sck high 0 -- ns s lave mode ; see f ig .19 t c sck cycle time f s = 48 khz 325.6 - 651.2 ns t ch sck high time f s = 48 khz 116 -- ns t cl sck low time f s = 48 khz 116 -- ns t su ws and sd1 inputs set-up time before sck high 30 -- ns t h1 ws and sd1 inputs hold time after sck high 0 -- ns t h2 sd1 and sd2 outputs hold time after sck high 66 -- ns t d sck delay time until sd1 and sd2 outputs valid -- 223 ns symbol parameter conditions min. typ. max. unit
may 1994 36 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 timing characteristics master/slave mode transition; see fig.20 t sh syncdai high time 1280 -- ns t d1 ws and sck outputs enabled after syncdai low 140 -- ns t d2 ws and sck outputs disabled before syncdai low 140 -- ns t d3 sd1 output disabled before syncdai high 250 -- ns t d4 sd1 output enabled after syncdai low 790 -- ns timing l3 interface; see fig.24 a ddressing mode t ch l3clk high time 210 -- ns t cl l3clk low time 210 -- ns t d1 l3mode low delay time until l3clk high 190 -- ns t su l3data input set-up time before l3clk high 190 -- ns t h1 l3data input hold time after l3clk high 30 -- ns t h2 l3clk high hold time before l3mode high 190 -- ns t d2 l3mode low delay time until l3data disabled 0 - 50 ns t d3 l3mode high delay time until l3data enabled 0 - 50 ns symbol parameter conditions min. typ. max. unit
may 1994 37 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 notes 1. the crystal frequencies 22.5792 mhz 200 10 - 6 mhz and 24.5760 mhz 200 10 - 6 mhz must track each other in frequency with an accuracy of 200 10 - 6 mhz. for example if the 24.5760 mhz clock is 150 10 - 6 mhz fast, then the range of the 22.5792 mhz clock becomes - 50 10 - 6 mhz and +350 10 - 6 mhz 2. timing values only valid for internally generated fs256. d ata mode ; see f ig .25 t ch l3clk high time 210 -- ns t cl l3clk low time 210 -- ns t d1 l3mode delay time until l3clk high 190 -- ns t d2 l3mode delay time until l3data enabled 0 - 50 ns t d3 l3mode delay time until l3data valid -- 380 ns t su l3data set-up time before l3clk high 190 -- ns t h1 l3data input hold time after l3clk high 30 -- ns t h2 l3data output hold time after l3clk high 120 -- ns t d4 l3clk delay time until l3data output valid not between data bits 7 and 8 -- 360 ns between data bits 7 and 8 -- 530 ns t h3 l3clk high hold time before l3mode low 190 -- ns t d5 l3mode low delay time until l3data output disabled 0 - 50 ns t ml l3mode low time between data words 190 -- ns symbol parameter conditions min. typ. max. unit
may 1994 38 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 package outline handbook, full pagewidth x a b 10.1 9.9 12.9 12.3 0.15 m b 0.40 0.20 pin 1 index 1 44 34 33 23 22 11 0.40 0.20 0.15 m a 0.8 12 0.8 10.1 9.9 12.9 12.3 s 0.1 s seating plane 1.2 0.8 (4x) 1.2 0.8 (4x) 0.95 0.55 mbb944 - 2 detail x 0.85 0.75 0.25 0.14 2.10 1.70 0 to 10 o 1.85 1.65 0.25 0.05 fig.28 plastic quad flat-pack, 44-pin (short) (qfp44sl). dimensions in mm.
may 1994 39 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 soldering plastic quad ?at-packs b ywave during placement and before soldering, the component must be fixed with a droplet of adhesive. after curing the adhesive, the component can be soldered. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 c within 6 s. typical dwell time is 4 s at 250 c. a modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. b y solder paste reflow reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. dwell times vary between 50 and 300 s according to method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 min at 45 c. r epairing soldered joints ( by hand - held soldering iron or pulse - heated solder tool ) fix the component by first soldering two, diagonally opposite, end pins. apply the heating tool to the flat part of the pin only. contact time must be limited to 10 s at up to 300 c. when using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 c. (pulse-heated soldering is not recommended for so packages.) for pulse-heated solder tool (resistance) soldering of vso packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
may 1994 40 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. the digital compact cassette logo is a registered trade mark of philips electronics n.v.
may 1994 41 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 notes
may 1994 42 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 notes
may 1994 43 philips semiconductors preliminary speci?cation stereo ?lter and codec saa2003 notes
philips semiconductors philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40 783 749, fax. (31)40 788 399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970). tel. (011)821-2327, fax. (011)829-1849 canada: integrated circuits: tel. (800)234-7381, fax. (708)296-8556 discrete semiconductors: 601 milner ave, scarborough, ontario, m1b 1m8, tel. (0416)292 5161 ext. 2336, fax. (0416)292 4477 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. (571)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032)88 2636, fax. (031)57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (9)0-50261, fax. (9)0-520971 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01)4099 6161, fax. (01)4099 6427 germany: philips components ub der philips g.m.b.h., p.o. box 10 63 23, 20043 hamburg, tel. (040)3296-0, fax. (040)3296 213. greece: no. 15, 25th march street, gr 17778 tavros, tel. (01)4894 339/4894 911, fax. (01)4814 240 hong kong: philips hong kong ltd., components div., 6/f philips ind. bldg., 24-28 kung yip st., kwai chung, n.t., tel. (852)424 5121, fax. (852)428 6729 india: philips india ltd, components dept, shivsagar estate, a block , dr. annie besant rd. worli, bombay 400 018 tel. (022)4938 541, fax. (022)4938 722 indonesia: philips house, jalan h.r. rasuna said kav. 3-4, p.o. box 4252, jakarta 12950, tel. (021)5201 122, fax. (021)5205 189 ireland: newstead, clonskeagh, dublin 14, tel. (01)640 000, fax. (01)640 200 italy: philips components s.r.l., viale f. testi, 327, 20162 milano, tel. (02)6752.3302, fax. (02)6752 3300. japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5028, fax. (03)3740 0580 korea: (republic of) philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)794-5011, fax. (02)798-8022 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: philips components, 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb tel. (040)783749, fax. (040)788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546. philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)14163160/4163333, fax. (01)14163174/4163366. singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., components division, 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382. thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319. turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 2770, fax. (0212)269 3094 united kingdom: philips semiconductors limited, p.o. box 65, philips house, torrington place, london, wc1e 7hd, tel. (071)436 41 44, fax. (071)323 03 42 united states: integrated circuits: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 discrete semiconductors: 2001 west blue heron blvd., p.o. box 10330, riviera beach, florida 33404, tel. (800)447-3762 and (407)881-3200, fax. (407)881-3300 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 for all other countries apply to: philips semiconductors, international marketing and sales, building baf-1, p.o. box 218, 5600 md, eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd31 ? philips electronics n.v. 1994 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 513061/1500/01/pp44 date of release: may 1994 document order number: 9397 731 40011

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